FIG. 7 is a diagram illustrating an example of the constitution of a current driver IC in the prior art for driving an active type EL panel. This current driver IC has 160 output channels, and it outputs driving currents having 256-step levels according to 8-bit pixel data from the various output channels to the pixels of the display panel. The current driver IC shown in FIG. 7 has current source CS2, n-type MOS transistor Qc1, output circuits U-i, . . . , U-160, output terminals To1, To2, To3, . . . , and control terminal T1.
The terminal on one side of current source CS2 is connected to control terminal T1, and the terminal on the other side is connected to the drain of transistor Qe1. Control terminal T1 is connected via externally connected resistor R2 to power supply voltage AVDD. Current source CS2 outputs reference current Iref according to externally connected resistor R2 to the drain of transistor Qc1 . The gate and drain of transistor Qc1 are connected to common node Nd, and its source is connected to reference potential AVSS. Output circuit U-1 (here, 1 represents any integer in the range of 1–160) has n-type MOS transistors Qa0–Qa7, and n-type MOS transistors Qb0–Qb7.
Transistors Qa0–Qa7 form a current mirror circuit together with transistor Qc1. The gates of transistors Qa0–Qa7 are connected to common node Nct, and their sources are connected to reference potential AVSS. The ratios of the sizes of transistors Qa0–Qa7 are proportional to powers of 2. That is, the size of transistor Qa1 is twice that of transistor Qa0; transistor Qa2 is 4 times the size of transistor Qa0; transistor Qa3 is 8 times the size of transistor Qa0; transistor Qa4 is 16 times the size of transistor Qa0; transistor Qa5 is 32 times the size of transistor Qa0; transistor Qa6 is 64 times the size of transistor Qa0; and transistor Qa7 is 128 times the size of transistor Qa0.
Transistors Qb0–Qb7 form switches that connect the drains of transistors Qa0–Qa7 to output terminal To1. The drain of transistor Qaj (where j is any integer in the range of 0–7) is connected via transistor Qbj to output terminal To1. Bit signal bj is input to the gate of transistor Qbj. When bit signal bj is “1” (high level), transistor Qbj is ON, and, when bit signal bj is “0” (low level), transistor Qbj is OFF.
With this constitution, reference current Iref according to the resistance value of externally connected resistor R2 flows in current source CS2. As reference current Iref flows to transistor Qc1, the gate voltage of transistor Qc1 according to the reference current Iref is generated at node Nc1.
The voltage generated at node Nd is commonly applied to the gates of transistors Qa0–Qa7. Because transistors Qa0–Qa7 have a size ratio proportional to powers of 2, 8 types of currents with power of 2 weighting (×1, ×2, ×4, ×8, ×16, ×32, ×64, ×128) flow in the transistors. Transistors Qb0–Qb7 are set ON/OFF according to the 8-bit pixel data {b0, . . . , b7}. As a result, the currents among the 8 types of currents with power of 2 weighting selected according to the pixel data {b0, . . . , b7} are synthesized at output terminal To1, and the obtained current is fed to the pixel as driving current. Because the driving current has a 256-step magnitude according to the 8-bit pixel data, using it in driving the pixel makes it possible to adjust the luminance of the pixel to 256 levels.
With current driver IC shown in FIG. 7, however, when transistor Qbj is switched from ON to OFF, the current path of transistor Qa1 is completely cut off Consequently, when the pixel data of the various output channels are set at various values, the current consumed in output circuits U-1 to U-16 are also changed to various values. Because variation of the consumed current causes variation in the voltage of the power supply line, fluctuation occurs in the driving current between output channels. Also, when plural current driver ICs are used to drive a single display panel, because the currents consumed by the different ICs are different, the voltage of the power supply line for each IC varies, and fluctuation occurs in the driving current between ICs. When fluctuation occurs in the driving current, fluctuation in luminance, lines, etc., occur in the picture, so that the image quality is degraded. This is undesirable. For example, assuming a certain IC displays white for all of the pixels, while the adjacent IC displays black for all of the pixels, and then the next adjacent IC displays white for all of the pixels, the output currents of the first and third ICs become the maximum, and the output current of the second IC becomes zero.
Also, for current driver IC shown in FIG. 7, when transistor Qbj is switched ON/OFF, the drain voltage of transistor Qaj also varies. For example, as shown in FIG. 8, when bit signal b7 (FIG. 8(A)) is set at the high level, the voltage of node Na7 rises to a certain voltage, and this voltage is held during the period of output of driving current to the pixel. However, when bit signal b7 changes from the high level to the low level, because transistor Qb7 is OFF, transistor Qa7 cannot maintain a constant current, and the voltage of node Na7 falls to reference potential AVSS. Consequently, the voltage of node Na7 varies significantly when transistor Qb7 is switched ON/OFF (FIG. 8(B)).
Because the drain voltage of transistors Qb0–Qb7 varies as described, the voltage of node Nd varies due to the influence of the parasitic capacitance between drain and gate (FIG. 8(C)). The voltage of node Nd influences the output current of each output channel. Consequently, since the voltage varies, the time needed to stabilize the driving current increases, and this is undesirable. Variation in the voltage of node Nd is greatest when all of transistors Qbj are turned ON/OFF at the same time. Also, in conjunction with increased precision of the gradation data of 8 bits or higher and increase in the number of output transistors Qaj, the load of node Nc I increases, and more time is needed to stabilize the driving current. In order to solve this problem, it has been proposed that the size of transistor Qc1 that forms the current mirror circuit be made larger to increase the ratio of transistors Qc1 and Qaj. However, this leads to an increase in reference current Iref and in the size of the layout area.
A general object of the present invention is to solve the aforementioned problems of the prior art by providing a type of current driver that can control variation in the voltage and consumed current of node Nd in conjunction with variation in the setting value of the driving current.